Interrupt USB Host Endpoint Set Register
EP1DRQS | This bit sets EP1DRQ bit. If this bit is written to ‘1’, EP1DRQ is set to ‘1’. However, if this bit is written with ‘0’, its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is ‘1’, EP1DRQ can’t be set to ‘1’. |
EP1SPKS | This bit sets EP1SPK bit. If this bit is written to ‘1’, EP1SPK is set to ‘1’. However, if this bit is written with ‘0’, its value is ignored. Note: If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is ‘1’, EP1SPK can’t be set to ‘1’. |
EP2DRQS | This bit sets EP2DRQ bit. If this bit is written to ‘1’, EP2DRQ is set to ‘1’. However, if this bit is written with ‘0’, its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is ‘1’, EP2DRQ can’t be set to ‘1’. |
EP2SPKS | This bit sets EP2SPK bit. If this bit is written to ‘1’, EP2SPK is set to ‘1’. However, if this bit is written with ‘0’, its value is ignored. Note: If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is ‘1’, EP2SPK can’t be set to ‘1’. |